Archives

The AMC529 provides two Analog Devices AD9129. Each chip core is based on a quad switch architecture that enables dual-edge clocking operation, effectively increasing the DAC update rate to 5.7 GSPS when configured for Mix-Mode or 2x interpolation. The high dynamic range and bandwidth enable multi-carrier generation up to 4.2 GHz. The on-board Virtex-7 690T provides signal processing capability for complex waveform generation, appropriate for applications such as SDR, ATE and jamming.

The AMC ports 12-15 and 17-20 are optionally routed to the FPGA from the AMC connector, providing the user with flexibility to support custom high-bandwidth interconnects between compatible FPGA modules (depending on backplane capabilities). The FPGA is supported byFLASH memory for boot image storage, four banks of QDR-II+ for fast data buffering and a further bank of DDR3 for local data.

TCLKA-D are routed to the FPGA via an on-board clock and jitter cleaner while FCLK is routed directly. The module includes a very flexible clocking sub-system, supporting internal or external (backplane or FMC connector) clock source with internal PLL/jitter cleaner.

The AMC529 is available in both air-cooled (MTCA.0 and MTCA.1) and rugged conduction cooled(MTCA.2 or MTCA.3) versions.

The AMC526 provides dual-channel ADC with sample rates up to 2.6 GSPS, making it suitable for signal capture/analysis applications such as COMINT/SIGINT, radar, research and instrumentation. The on-board Virtex-7 690T is suitable for local signal processing and data reduction prior to transfer out via the backplane using PCIe, SRIO or Ethernet.

The AMC ports 12-15 and 17-20 are optionally routed to the FPGA from the AMC connector, providing the user with flexibility to support custom high-bandwidth interconnects between compatible FPGA modules (depending on backplane capabilities). The FPGA is supported by FLASH memory for boot image storage, four banks of QDR-II+ for fast data buffering and a further bank of DDR3 for local data.

TCLK A-D are routed to the FPGA via an on-board clock and jitter cleaner while FCLK is routed directly. The module includes a very flexible clocking sub-system, supporting internal or external (backplane or front panel) clock source with internal PLL/jitter cleaner.

The AMC526 is available in both air-cooled (MTCA.0 and MTCA.1) and rugged conduction cooled(MTCA.2 or MTCA.3) versions.

The AMC524 provides a Direct Digital Synthesizer (DDS) capable of generating a frequency agile analog sinusoidal waveform (up to 1.0 GHz). The chipset includes a PLL for clock cleaning, along with a versatile internal timing and control mechanism. The unit supports fast frequency hopping and a linear sweep mode of frequency, phase or amplitude.

The AMC ports 0-15 are all routed to the FPGA from the AMC connector, providing the user with flexibility to support standard base and fabric interface or custom high-bandwidth interconnects (depending on backplane capabilities). The FPGA is supported by 1 GB FLASH memory for boot image storage and dual banks of DDR3 for local data storage.

TCLK A-D and FCLK are routed to the FPGA via an on-board clock and jitter cleaner. The module supports internal or external clocking. The modules allows for RF Clock synthesis for the DAC and the ADC to come from the front panel or from the on-board wideband PLL.

The AMC524 is available in both air-cooled (MTCA.0 and MTCA.1) and rugged conduction cooled (MTCA.2 or MTCA.3) versions.