Highlights:

• The multi-part virtual event will show attendees how to take advantage of PICMG’s next-generation computer on module specification family for intelligent edge use cases.
• Sessions will address how the Mini form factor enhances performance in mobile-friendly deployments, new features like the updated COM-HPC connector, and a new Carrier Design Guide.
• Attend for free on June 4^th at 14:00 UTC at https://t.ly/COM-HPCMiniAcademy.

MAY 29, 2024 — WAKEFIELD, MA. PICMG, the consortium driving open standards for modular, scalable computing, will be hosting a COM-HPC Mini Academy on Tuesday, June 4 at 14:00 UTC. This multi-part virtual event will span four sessions and introduce participants to the new COM-HPC Mini form factor’s features, including details of the Mini’s updated Carrier Design Guide, as well as examine use cases, design questions, and deployment challenges.

“Between converged network rollouts and advances in artificial intelligence, the hardware requirements for edge computing have changed,” said Doug Sandy, CTO of PICMG. “Modern edge workloads need a combination of high-end computing, power consumption management, and low-latency data transmission. The COM-HPC Mini addresses these requirements, and our Mini Academy will teach developers everything they need to know about how the specification brings the intelligent edge to life.”

The event will be divided into four sessions covering the following topics:

• How COM-HPC Mini improves performance in mobile-friendly deployments.
• The importance of support for CPU, GPU, FPGA and heterogenous processor architectures in diverse edge applications.
• Details on new features in COM-HPC and how they enable greater bandwidth, lower latency, more rugged designs, and interoperable high-speed chip-to-memory interconnects.
• How the updated Carrier Design Guide streamlines development and deployment of cost-optimized, low-to-mid volume production runs.

More details on each session can be found below:

Session 1: June 4^th at 14:00 UTC—What’s New in COM-HPC?

The first Mini Academy session, co-hosted by representatives from congatec, Samtec, and the University of Bielefeld, provides an update on COM-HPC and how it can help organizations transform their edge infrastructure. Alongside updates to the COM-HPC specification family, the session will explore potential PCIe Gen 6 support, CXL 3.1 compatibility, and Functional Safety (FuSa) capability.

Session 2: June 4^th at 14:30 UTC—Introducing COM-HPC Mini

Co-presented by Richard Pinnow of ADLink and Christian Engels of Avnet Embedded, this session will detail how COM-HPC Mini provides system architects with greater speed and performance in a smaller form factor. Participants can expect a review of the new specification’s electromechanical features, followed by demonstrations of how they can leverage those features for far edge mobile and battery powered use cases, such as AMRs, HMIs, drones, and robotic controllers.

Session 3: June 4^th at 15:00 UTC—Exploring the COM-HPC Mini Design Guide

Presented by Kontron’s Peter Hunold, this session introduces the updated Carrier Design Guide developed specifically for the COM-HPC Mini specification. Participants will be given an overview of how the COM-HPC Design Guide has changed from previous versions. The session will conclude by demonstrating how to design in advanced signals, like multiplexed USB 4.0 and how to quickly and efficiently produce Gerber files that define lasting COM-based systems.

Session 4: June 4^th at 15:30 UTC—The COM-HPC Mini Academy: A Multi-Vendor Outlook Panel

Co-hosted by several of the suppliers responsible for developing the COM-HPC Mini specification, this discussion panel will field questions from attendees about designing and deploying the new standard. Participants will also learn about the differences between COM Express and COM-HPC, along with best practices for designing the COM-HPC Mini into real-world applications. The session will then conclude with insight into PICMG’s technology roadmaps.

Going Beyond the Intelligent Edge

“First ratified in 2021, COM-HPC was designed to address the challenges and fulfill the requirements of embedded system architects,” explained Sandy. “COM-HPC Mini continues this trend, introducing a new form factor and features like expanded connectivity support, efficient thermal management, and soldered memory.”

“Open, interoperable, and available from multiple suppliers, COM-HPC Mini provides a path forward for edge computing that will remain relevant for decades,” he added, inviting anyone interested in learning more about COM-HPC Mini and other specifications to visit PICMG’s website.

Recordings of the COM-HPC Mini Academy sessions will be available on-demand for those unable to attend the live event.

Learn More

• Event Registration: https://t.ly/COM-HPCMiniAcademy
• COM-HPC Overview: https://www.picmg.org/openstandards/com-hpc/
• Carrier Design Guide: https://www.picmg.org/wp-content/uploads/PICMG_COM-HPC_CDG_R2_1.pdf
• COM-HPC Mini: https://www.picmg.org/openstandards/com-hpc

About PICMG

Founded in 1994, PICMG is a not-for-profit 501(c) consortium of companies and organizations that collaboratively develop open standards for high performance industrial, Industrial IoT, military & aerospace, telecommunications, test & measurement, medical, and general-purpose embedded computing applications. There are more than 150 member companies that specialize in a wide range of technical disciplines, including mechanical and thermal design, single board computer design, high-speed signaling design and analysis, networking expertise, backplane, and packaging design, power management, high availability software and comprehensive system management.

Key standards families developed by PICMG include COM-HPC, COM Express, COM-HPC Mini, CompactPCI, AdvancedTCA, MicroTCA, AdvancedMC, CompactPCI Serial, InterEdge, ModBlox7, SHB Express, MicroSAM, and HPM (Hardware Platform Management). For more information, visit https://www.picmg.org.

Highlights:

• Carrier Design Guide helps hardware engineers design application-specific carrier boards for COM-HPC-based systems.
• Revision 2.2 of the Carrier Design Guide introduces new diagrams, figures, and design notes for COM-HPC Mini.
• Document contains technical materials such as interface schematics and practical guidance on design rules.

WAKEFIELD, MA. PICMG, a consortium for open hardware specifications, has released revision 2.2 of the COM-HPC Carrier Design Guide. This comprehensive document contains interface schematics, diagrams, design rules and requirements, and more for PCB layout engineers and hardware developers looking to create application-specific carrier boards that pair with COM-HPC modules.

Revision 2.2 of the Design Guide includes updates to address the new COM-HPC 2.1 specification, nicknamed COM-HPC Mini, which is the 95 mm x 60 mm platform that uses one less connector compared to its fellow COM-HPC form factors, but still delivers 400 pins for carrying high-speed signals from the processor module to carrier boards.

“Designing a carrier board can be a complex and time-consuming process, but the COM-HPC Design Guide helps streamline that process” says Peter Hunold, head of hardware engineering at Kontron Europe GmbH and editor of the COM-HPC working group. “It serves as an excellent complement to the COM-HPC base specification, as well as, for revisions like COM-HPC 2.1 that introduced the new “Mini” form factor and vendor documentation.”

What’s New in COM-HPC Carrier Design Guide Revision 2.2

Revision 2.2 of the Carrier Board Design Guide primarily focuses on the COM-HPC Mini, a small form factor expansion of the COM-HPC standard first announced in 2022. This new guide clarifies the differences between COM-HPC Client and COM-HPC Mini carrier board requirements, with examples that illustrate modifications necessary to move from Client- to Mini-compatible designs.

The Design Guide 2.2 release also introduces information on the Intel JHL9040R USB4 Retimer, which replaces the JHL8040R in Rev 2.1. In addition to updated references, the document includes Intel JHL9040R block diagrams for both COM-HPC Client and COM-HPC Mini designs.

“Designing hardware to support new and emerging workloads is becoming progressively more challenging. Open standards such as COM-HPC help businesses overcome those challenges,” says Christian Eder, director of market intelligence at congatec. “They considerably reduce time-to-market for even the most sophisticated applications, especially with documentation to streamline the design process.”

Learn More

The COM-HPC Carrier Design Guide revision 2.2 can be downloaded free of charge from PICMG’s website. For more information on the Design Guide, the COM-HPC standard, and other related specifications, visit:

• COM-HPC Design Guide Revision 2.2: https://www.picmg.org/wp-content/uploads/PICMG_COMHPC_CDG_R2_2.pdf
• COM-HPC Specification Documents: https://www.picmg.org/shop/
• COM-HPC Overview: https://www.picmg.org/openstandards/com-hpc/
• PICMG Design Guides: https://www.picmg.org/resources/design-guides/

About PICMG

Founded in 1994, PICMG is a not-for-profit 501(c) consortium of companies and organizations that collaboratively develop open standards for high performance industrial, Industrial IoT, process control and automation, military & aerospace, telecommunications, test & measurement, medical, and general-purpose embedded computing applications. There are more than 150 member companies that specialize in a wide range of technical disciplines, including mechanical and thermal design, single board computer design, high-speed signaling design and analysis, networking expertise, backplane, and packaging design, power management, high availability software and comprehensive system management.

Key standards families developed by PICMG include COM-HPC, COM Express, CompactPCI, CompactPCI Serial, MicroTCA, AdvancedMC, AdvancedTCA, InterEdge, ModBlox7, HPM (Hardware Platform Management), MicroSAM, and SHB Express. For more information, visit https://www.picmg.org.

PICMG: Can you describe your work outside of PICMG as well as the role you played in development of the COM-HPC specification? 

JENS: I am currently engaged in research at Bielefeld University, focusing on the development of heterogeneous and reconfigurable computing technologies for a wide range of applications. These include the Internet of Things (IoT), edge computing, cloud computing, and high-performance computing (HPC).

My involvement with the early stages of the COM-HPC specification centered on leading the development of the Platform Management Interface Specification and expanding the Embedded EEPROM Specification for COM-HPC. 

PICMG: You recently raised awareness about the CXL standard within the COM-HPC community. What is CXL and why is it relevant for PICMG COM-HPC developers and users?

JENS: CXL, or Compute Express Link, is a high-speed, high-capacity interconnect standard that facilitates efficient communication between CPUs, memory, and peripherals using the PCIe physical layer. Its support for cache coherency, disaggregation, and scalable architectures makes it a compelling choice for modular form factors like COM-HPC, driving its popularity among developers and users seeking advanced computing solutions.

PICMG: Why is CXL 3.1 significant in the context of COM-HPC? What use cases or capabilities will it drive in the COM-HPC ecosystem?

JENS: CXL introduces features that cater to the demanding requirements of cloud and high-performance computing systems. Its emphasis on scalable architectures, disaggregation, and cache coherency is particularly relevant for COM-HPC, offering the potential to revolutionize the way modular computing platforms are designed and utilized. 

The integration of CXL into COM-HPC could facilitate the development of more sophisticated computing solutions, enabling the seamless coupling of specialized accelerators and the establishment of cache-coherent multi-socket systems. These advancements promise to unlock new possibilities for COM-HPC applications, ranging from data-intensive analytics to AI and machine learning workloads, driving innovation in modular computing technologies.

PICMG: Given that CXL targets PCIe, has it been compatible with COM-HPC to date?

JENS: The relationship between CXL and COM-HPC is fundamentally influenced by CXL’s reliance on the PCIe physical layer for connectivity. This means that while direct compatibility between previous versions of CXL and COM-HPC has not been explicitly defined, the architectural underpinnings allow for potential integration. 

The absence of CXL in the current COM-HPC specification, coupled with the lack of support in existing modules, suggests that the integration of CXL represents a forward-looking opportunity for enhancing COM-HPC. Such integration is anticipated to require minimal modifications to the specification, paving the way for future advancements in modular computing.

PICMG: What does the COM-HPC community need to know about the CXL market or technical requirements to capitalize on the opportunity?

JENS: To fully leverage the potential that CXL brings to the COM-HPC community, it is crucial to understand the intricacies of CXL’s market dynamics and technical specifications. This involves a deep dive into the architecture of CXL, including its device types—such as Type 1 for I/O devices, Type 2 for cache-coherent devices, and Type 3 for memory expander devices. Additionally, understanding the topology options that CXL supports, including switch-based topologies for larger, more complex systems, can empower developers to design COM-HPC solutions that are both innovative and future-proof. 

Staying abreast of the evolving CXL specifications and market trends will enable the COM-HPC community to identify new opportunities for integration and application, ensuring that COM-HPC modules remain at the forefront of technological advancement.

PICMG: What are you and Bielefeld University doing with respect to CXL today?

JENS: We are working on integrating CXL within the RISC-V ecosystem, a venture that holds promising implications for the future of computing architectures. Our work focuses on the development of innovative bridge technologies that facilitate communication between the RISC-V Coherent Hub Interface (CHI) and CXL, using FPGA-based modules, which we refer to as microservers. 

This endeavor is not just about bridging two technical standards; it’s about creating a foundation for next-generation computing platforms that can seamlessly integrate diverse processing and memory resources. By developing these bridges, we aim to enable more efficient, scalable, and flexible computing architectures that can cater to the demanding requirements of modern applications, ranging from AI and machine learning to big data analytics.

PICMG: Where can interested parties go to find more information on CXL?

JENS: The CXL Consortium website serves as the primary repository of knowledge. This platform not only provides access to the official CXL specifications and technical documents, but also offers insights into the latest developments, industry adoption stories, and educational resources.

More Information:
• Compute Express Link: https://computeexpresslink.org
•*PICMG COM-HPC Overview: https://www.picmg.org/openstandards/com-hpc
•*PICMG Platform Management Interface Specification: https://www.picmg.org/product/com-hpc-platform-management-interface-specification