COM-HPC Overview

COM-HPC™ is the soon-to-be-released PICMG standard for high-performance Computer-on-Modules (COMs). The pinout and majority of the functionality were recently officially approved.

Final PICMG ratification of the COM-HPC specification is scheduled for the Q3 2020; in the meantime, the PICMG subcommittee already approved two key aspects in November 2019: the physical footprints and the pinout. This up-front approval enables companies involved in the definition of the specification to present their first products on the market shortly after the standard’s official ratification. The information that may be released to the public until that moment is strictly limited.

Higher performance, more interfaces

The need for a new specification to complement COM Express is easily explained: As a result of the digital transformation, demand for embedded computers to provide high-speed performance is growing. To serve the new class of embedded edge servers, scalability must be limitless. With its 440 pins, COM Express does not have enough interfaces for powerful edge servers. The performance of the COM Express connector is also slowly approaching its limits: While COM Express can easily handle the 8.0 GHz clock speed and 8 Gbit/sec throughput of PCIe Gen 3, the verdict is still out regarding whether the connector meets certain technological advances such as PCIe Gen 4.

Headless embedded server performance

The need for ultra-high embedded edge performance and extended connectivity is most pressing in the new class of headless edge servers that are increasingly used as distributed systems in industrial applications for harsh environments and over extended temperature ranges. An example of the need for high performance on the edge: An autonomous vehicle uses vision and AI logic to establish situational awareness. It simply cannot wait for an algorithm to be computed in the cloud when things get tricky; it must be able to react instantly. The same idea applies to collaborative robots. Both of these examples would require systems to provide at least 10 GbE connectivity as well as the ability to use a large number of parallel computing units – for example, to preprocess imaging sensor data or to execute complex deep learning algorithms. Today, GPGPUs are increasingly being used to execute such flexible and multifunctional tasks. Often replacing FPGAs and DSPs, they need high-speed connectivity towards the central CPU cores, with this need increasing with the complexity of the tasks. With their many PCIe lanes, COM-HPC systems can accommodate significantly more accelerator cards for further performance increases than COM Express ever could.

Massive parallel data processing

A setup that combines powerful CPUs and massive parallel data processing capacity is also required in medical imaging, where the use of artificial intelligence is increasing to support medical diagnosis on the basis of existing findings. The same performance requirements apply to the countless vision systems used in industrial inspection systems and to public video surveillance systems. The entire field of Industry 4.0 applications also needs more powerful connectivity, as more and more formerly standalone machines and systems are being networked. All this connection drives up demand for high-speed interfaces in embedded systems to implement high-performance Internet solutions, including TSN support for tactile real-time behavior.

In addition, more workloads need to be consolidated in a single system: Next to data preprocessing in vision systems and deep learning, this includes firewalls and sniffing systems for intrusion detection, which must process virtually identical loads parallel to the running applications. This workload combination doubles requirements and calls for the use of hypervisor technologies for real-time capable virtual machines such as the RTS Hypervisor from Real-Time Systems. Other applications include data grabbers for automotive test systems and measurement technology for 5G as well as industrial storage systems with fast NVMe memory connected via PCIe. Edge logic for 5G radio towers and modular blades in industrial server racks can also benefit from high-performance COMs.

Up to one terabyte of RAM

COM-HPC will be covering these high-speed performance requirements with up to 100 GbE, up to 32 Gb/s PCIe Gen 4 and Gen 5, plus up to eight DIMM sockets and high-speed processors with more than 200 watts of power. The new standard distinguishes two basic variants: headless COM-HPC server modules, which can also be called Server-on-Modules, and COM-HPC client modules, which follow the concept of COM Express Type 6 Computer-on-Modules.

COM-HPC Server-on-Modules will be able to host a massive 1.0 terabytes of RAM with their eight DIMM sockets. They will also run up to 8x 25 GbE and support up to 64 PCIe Gen 4 or Gen 5 lanes – i.e., an I/O performance of up to 256 Gigabytes/sec (GB/sec). Such ultrafast connectivity falls within the embedded edge server class, with the new PCIe lanes offering transfer rates of more than 32 Gigabit/sec (Gbit/sec) with PCIe Gen 5. This needed level of performance can be directly implemented via high-performance interfaces, since components with the ability to transfer 28 Gbit/sec Non-Return-to-Zero (NRZ) are already available. In addition, up to two extremely powerful USB 4 interfaces are planned via the 800 pins.

Based on Thunderbolt 3.0, these interfaces correspond to about 5 GB/sec and run about twice as fast as USB 3.2 with a maximum of 20 Gb/sec, which is also supported up to 2x. An additional four USB 2.0 interfaces complete the USB choices on COM-HPC server modules. Next to 2x native SATA, support for eSPI, 2xSPI, SMB, 2x I2C, 2xUART, and 12 GPIOs is also provided to integrate simple peripherals and standard communication interfaces, for example for service purposes.

Server-class board management

Another new feature of COM-HPC is the integrated system management interface. This software interface, which is currently being defined by the PICMG subcommittee, aims to include a small subset of the powerful and complex IPMI definition in the COM-HPC specification to enable easy implementation of full server functionality. Thanks to this interface, COM-HPC will offer real edge-server functions that can be widely expanded by integrating suitable server-class board management controllers (BMC) on carrier boards. Relevant carrier board design guides will be needed to help newcomers to the standard get started.

The specification will further offer the possibility to develop COM-HPC device modules for graphics processors or FPGAs. For this purpose, the specification defines PCIe clock inputs so that COM-HPC modules can also be used as clients. This capability makes it possible to design flexible and compact heterogeneous computing solutions without a need for complex raiser cards; in contrast, traditional graphics cards are developed for PCIe sockets that are mounted at a 90-degree angle on the motherboard. They also offer significantly fewer connectivity options. The same applies to the alternative of MXM3 graphics cards, as they also have only 314 pins. With COM-HPC enabling extremely thin modular designs, also for the GPGPU, it then becomes possible to design thin slot cards for rack systems that offer both COM-HPC server modules and accelerator modules based on GPGPUs, FPGAs, or DSPs. Matching solutions for all three accelerator module variants are already being developed, so that COM-HPC is no longer just a standard for embedded edge server processors, but can also be used for GPGPU, FPGA, and DSP expansion.

A boost to 800 pins

Next to this ultra-high-performing embedded edge server class, which sets an entirely new standard for robust embedded computing, the second category of COM-HPC client modules positions itself somewhat more discreetly above the COM Express Type 6 specification. As the smaller footprint can accommodate only up to four SO-DIMM sockets, it is mainly the number of pins that makes a key difference: 800 pins clearly offer significantly more interface options than the 440 pins of COM Express. (Figure 3.)

Figure 3 | COM-HPC specifies two different pinouts for embedded computing servers and embedded computing clients.

But as long as COM Express can also handle PCIe Gen 4 – which can be assumed at least with regards to downward compatibility – developers of COM Express systems don’t have to switch to COM-HPC client modules. In addition to 49 PCIe lanes (COM Express Type 6 offers only 24), there are now for the first time two 25 GbE KR interfaces and up to two 10 Gb BaseT interfaces, significantly more than the current single GbE LAN.

Another attractive feature is the capability for one or two MIPI-CSI interfaces, which enable cost-effective camera connections for situational awareness and collaborative robotics. Many developers will also appreciate the convenient, versatile and extremely powerful USB 4.0 interfaces that are offered in addition to 4x USB 2.0. There will be up to four of them, to connect ultra-fast memory with up to 40 Gbps, or up to two 4K displays including power supply and integrated 10GbE network connection via a single USB-C cable. The graphics have also been tidied up. Support now includes 3x dedicated DDI interfaces. Specific designs for DisplayPort, DVI-I/VGA and DVI-I, HDMI, or DVI to LVDS converters are now executed on the carrier board. Further interfaces include 2x SoundWire and I2S as well as 2x SATA; eSPI, 2xSPI, SMB, 2x I2C, 2x UART, and 12 GPIOs round out the feature set.

SoundWire, which has been added as a new interface to the specification, will replace the currently used HDA interface. SoundWire is a MIPI standard that requires only two clock and data lines, with a clock rate of up to 2.288 MHz, to connect up to four audio codecs in parallel. Each codec receives its own ID which is evaluated.

OEMs that have a business relationship with one of the companies involved in the new specification can already start suitable carrier board designs as long as they keep them under NDA and do not share them with third parties. The new specification will only become available as an open standard after the official release.

Members of the PICMG COM-HPC subcommittee include the University of Bielefeld plus Acromag, ADLINK, Advantech, Amphenol, AMI, congatec, Elma Electronic, Emerson Machine Automation Solutions, ept, Fastwel, HEITEC, Intel, Kontron, MEN, MSC Technologies, N.A.T., nVent, Samtec, Schroff, SECO, TE Connectivity, Trenz Electronic, and VersaLogic. Adlink, congatec and Kontron are committee sponsors, while congatec marketing director Christian Eder acts as chairman of the COM-HPC committee. He has also played an important role in the development of the existing COM Express standard as draft editor. Stefan Milnor from Kontron and Dylan Lang from Samtec support Christian Eder in their functions as editor and secretary, respectively, of the PICMG COM-HPC committee.