Introduction
As the use of AI continues to grow across industry, mobility, and energy applications, the demand for computing performance, memory bandwidth, and advanced connectivity in embedded systems is increasing significantly. To address these requirements, the PCI Industrial Computer Manufacturers Group (PICMG) developed the Computer-on-Module for High Performance Computing (COM-HPC) standard. It enables the design of modern Computer-on-Modules (COMs) featuring high-performance processors, high-speed interfaces, and scalable I/O bandwidth.
As the natural successor to COM Express, COM-HPC was ratified in 2021 and is available in Client, Server, and Mini form factors. Typical applications range from autonomous robots and AI-assisted medical devices to machine vision, gaming, and data-intensive edge systems. With COM-HPC Revision 1.3, PICMG continues the evolution of the standard by integrating key next-generation technologies to meet the growing demands for performance, memory bandwidth, and design flexibility.
Fundamentals of COM-HPC
The COM-HPC specification defines three module classes: Client Size A, B, and C; designed for embedded, edge, and vision applications. Server Size D and E provide a significantly higher number of PCIe lanes, Ethernet interfaces, and memory resources for data-intensive workloads such as machine vision, industrial edge servers, and networking equipment.
With COM-HPC Revision 1.2, released in October 2023, the Mini form factor was introduced. Measuring only 95 mm × 70 mm, it was designed for space-constrained, energy-efficient, and rugged applications. Revision 1.2 also introduced support for state-of-the-art high-speed interfaces, including PCI Express Gen 5, USB4, 25 Gigabit Ethernet (GbE), and MIPI-CSI for camera integration.
Figure 1: COM-HPC modules are specified in Client Size A, B, and C, Server Size D and E, as well as the Mini form factor. (Source: PICMG)
Thanks to COM-HPC’s modular architecture, developers can independently upgrade computing performance through the COM, as well as the carrier board, in existing systems. This shortens development cycles while protecting investments in existing platforms over the long term.
However, the growing adoption of AI applications, edge analytics, and memory-intensive workloads places entirely new demands on embedded systems. Higher data rates, more efficient memory architectures, optimized power management, and greater flexibility in system integration are becoming increasingly important. At the same time, manufacturers are placing greater emphasis on establishing resilient supply chains and ensuring the long-term availability of components.
COM-HPC Revision 1.3 extends the standard with key next-generation technologies such as PCIe Gen 6 and Compute Express Link (CXL). At the same time, it improves power efficiency and provides additional flexibility for system design. Revision 1.3 remains fully backward compatible with revision 1.2, enabling developers to prepare existing platforms for new technologies, step–by–step, without fundamentally redesigning established hardware architectures.
Key Enhancements in COM-HPC 1.3
Revision 1.3 extends the COM-HPC specification with features designed to meet the requirements of modern embedded, edge, and server platforms. Its primary focus is on higher data rates, advanced memory architectures, improved power efficiency, and greater flexibility for system integration.
Performance & Interconnects
One of the most significant enhancements is support for PCI Express Gen 6. By doubling the data rate from 32 GT/s to 64 GT/s, the new interface places considerably higher demands on PCB layout, connectors, and signal integrity. To provide developers with a reliable foundation for high-speed designs, COM-HPC 1.3 introduces detailed signal budgets for the first time. These signal budgets define permissible electrical parameters along the entire signal path, simplifying the design of carrier boards and modules for next-generation high-speed applications.
Figure 2: COM-HPC connectors are designed for high-bandwidth applications and officially support PCIe Gen 6 as well as future CXL-based system architectures with Revision 1.3. (Source: PICMG)
By integrating PCIe Gen 6 capability into COM-HPC Client and Server form factors, the specification also enables support for Compute Express Link (CXL). CXL 3.x provides memory coherency, memory expansion, resource pooling, and improved performance for accelerator-based applications over the PCIe interface. Against the backdrop of rising Dynamic Random Access Memory (DRAM) costs and increasingly demanding AI workloads, CXL opens new opportunities to optimize resources while reducing overall system costs. Support for CXL requires corresponding processor or chipset support.
Power Efficiency & Power Management
Another major focus of COM-HPC 1.3 is improved power management. By introducing Modern Standby (S0ix), COM-HPC modules can transition more efficiently into low-power operating states. In addition, bidirectional PCIe Clock Request signals have been introduced to enable more efficient power management, while clock inputs can now also be configured as clock outputs. These enhancements simplify clock management, reduce routing complexity, and support power delivery more efficiently in complex embedded platforms.
Expanded I/O Capabilities
COM-HPC 1.3 also expands the functionality of the available I/O interfaces. It now supports C-PHY over MIPI-CSI, enabling modern image sensors to achieve higher data rates while improving pin efficiency. In addition, an extra clock input supports 2×2 camera configurations for D-PHY, making the specification particularly attractive for machine vision and multi-camera applications.
Figure 3: COM-HPC supports a comprehensive range of interfaces depending on the Server, Client, or Mini specification. (Quelle: PICMG/congatec)
COM-HPC 1.3 further expands the available system interfaces by introducing preferred assignments for specific GPIOs, enabling standardized use for functions such as system status monitoring and external device control. An additional I²S interface increases flexibility for audio and multimedia applications. Furthermore, the specification also expands the allowable DC input range to support server-class designs with higher power requirements. Optionally, the SMBus can now be used as an additional I²C interface, increasing the number of available control and management interfaces without requiring additional hardware.
Mechanics & Ecosystem
In addition to the electrical enhancements, COM-HPC 1.3 also updates the mechanical specification. New connector options, including non-BGA solder-column variants alongside traditional BGA connectors, provide designers and manufacturers with greater flexibility while improving mechanical robustness, manufacturing options, and supply-chain availability.
The new column-type technology offers several advantages:
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Uniform and reliable solder joints for long-term durability
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Generously sized contacts that ensure optimum solder joint thickness and a large wetting area
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Proven solder joint reliability according to IPC-9701 (-55°C to +125°C)
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Seamless compatibility with existing PCB layouts
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Greater manufacturing flexibility to support cost-efficient production
At the same time, Samtec, Amphenol, Hirose, and All Best have been ratified as additional connector suppliers. This not only increases flexibility in component sourcing but strengthens supply chain resilience.
Comparison: COM-HPC 1.2 vs. 1.3
COM-HPC 1.3 maintains full backward compatibility, preserving existing module and carrier board designs while protecting prior development investments. The standard continues to deliver a fundamental advantage by separating the compute module from the application-specific carrier board, enabling straightforward technology upgrades, scalable system architectures, and extended product lifecycles.
Primary additions accommodate next-generation high-performance platforms such as PCIe Gen 6, CXL, expanded signal budgets, Modern Standby, additional clocking options, C-PHY over MIPI-CSI, and enhanced I/O and connector options. Thus, for existing designs, no fundamental redesign is required. Instead, systems can be selectively prepared for higher data rates, more efficient memory architectures, improved power efficiency, and greater design flexibility.
Design and Implementation Considerations
For developers of existing COM-HPC platforms, COM-HPC 1.3 introduces minor changes to the fundamental module–carrier board architecture while significantly expanding capabilities for future designs. Carrier boards intended to support PCIe Gen 6 or CXL must meet the increased requirements for signal integrity and high-speed transmission channels.
To address these requirements, the specification introduces PCIe Gen 6-compliant channel and signal budgets for the first time. These define the permissible losses and electrical characteristics along the entire signal path, providing developers with a solid foundation for PCB layout and signal integrity analysis. Likewise, new clocking options and additional connector concepts increase flexibility when integrating complex high-speed systems.
Figure 4: Example of a COM-HPC Client module: congatec’s conga-HPC/cBLS integrates the processor, memory, and high-speed interfaces on a standardized Computer-on-Module and connects to the target application through an application-specific carrier board. (Quelle: congatec)
Developers can continue using existing carrier boards with COM-HPC 1.2-based modules while selectively implementing new features where they provide added value. This approach preserves existing platform investments while allowing new systems to be prepared step by step for PCIe Gen 6, CXL, and future generations of high-performance processors.
Conclusion
With Revision 1.3, PICMG continues to evolve the COM-HPC standard for the next generation of high-performance embedded and edge systems. While preserving the proven architecture and full backward compatibility, the new revision significantly expands the standard through technologies such as PCIe Gen 6, CXL, Modern Standby, and additional I/O, clocking, and connector options.
In doing so, the specification addresses today’s requirements for higher bandwidth and improved energy efficiency while preparing developers for future technologies such as memory-centric architectures and AI-driven applications. As a result, COM-HPC 1.3 further strengthens COM-HPC’s position as an open, scalable, and future-proof standard for high-performance embedded computing.