Under Development (Updated March 2016)

PICMG develops new standards and revises existing ones on an on-going basis. 

New standards come to life when members identify the need to create a new embedded computing standard for a particular market or application. This is a structured process, but is relatively simple to initiate. All it takes to begin the development process is an initial Statement of Work, sponsored by three or more Executive members, that describes the market need and a rough proposal of what a standard addressing that might look like. The process is then opened up for all members to participate in the actual engineering work and development. The broad technical skill set of the membership and the one-company-one-vote rule provide an excellent environment for the creating of successful and relevant industry standards.

Existing standards are updated when appropriate. This might be because new technology becomes available that would improve the performance or lower the cost of compliant products. Existing standards are also extended when a new market or application is identified that requires new or additional features. These extensions are usually created in the form of subsidiary specifications that provide additional detail or enhancements.

Standards Recently Released or Currently Under Development

CompactPCI Serial Revision 2

The CompactPCI Serial standard has become a popular platform for a variety of applications requiring modularity, high performance, and symmetric multi-processing. It is being used for a wide range of industrial control, communications, data acquisition, mil/aero, security, and medical applications. Using modern serial interfaces including Ethernet, SATA, and USB 2.0/3.0, CompactPCI Serial provides data transfer rate improvement of about 20x over original CompactPCI.

A technical subcommittee has just completed work on a second revision of this flexible platform. It increases capability by providing direct rear I/O over the P6 connector enabling economical low end solutions. Up to three complete CompactPCI Serial single board computers can co-exist on the same backplane and communicate via Ethernet without the need for bridges or switches. Full mesh systems with up to nine processors are still supported using the appropriate backplane topology. Backwards compatibility with existing CompactPCI and CompactPCI Serial boards is maintained, also via backplane topology.

This new revision was released in June, 2015

High Speed Ethernet Fabrics for MicroTCA and AMC.2

This effort is developing enumerated requirements that incorporate 10GBASE-KX4, 10GBASE-KR and 40GBASE-KR4 to the Common Option (ports 0 and 1), Fat Pipes (ports 4-7) and Extended Pipes (8-11) as defined in AMC.2 and used there and in all variants of MicroTCA.  A key goal of this activity is to guarantee backward compatibility with existing MTCA and AMC mechanicals and connectors.

The “Higher Speed Ethernet Fabrics for MicroTCA.0 and AMC.1” group is working on bringing 40GbE to MicroTCA systems.  The committee is currently working on completing signal integrity studies across the full interconnect channel.  S-parameter models for the backplane and AMC have been developed and simulated and work on the MCH is being completed. Combinations of 90 and 110 ohm impedance signal pairs are being simulated in order to see the behavior of all corner cases.  The committee will then compare the whole channel simulations with IEEE 40GBASE-KR4 requirements.

A 40G test backplane has already been designed and simulated as well as the AMC probe card.  The MCH probe card is also nearly complete.   In the coming months, it is expected that all the simulation and characterization will be complete.  From there, the MicroTCA.0 and AMC.1 specifications will be updated with the results, including the CRs (Change Requests) that have already been addressed.  These documents will then be submitted to the broader membership for review and approval.

100G Ethernet

Driven by the need for higher bandwidth in mobility, video and security, this effort will provide capacity improvement to the ATCA platform by incorporating 100Gb backplane Ethernet. Backward compatibility will be maintained. PICMG 3.1 R3.0 will update the PICMG 3.1 specification to incorporate 100GBASE-KR4 (NRZ) Ethernet signaling. The effort began in early 2015, and work is expected to be completed by the early 2016. It is being headed up by Doug Sandy, CTO of PICMG and Artesyn Embedded Computing. Doug headed up the successful 40G effort a couple of years ago.

This specification was sent to the PICMG membership for formal Member Review in March, 2016.

IPv6 for AdvancedTCA

Hardware Platform Management has been an integral part of ATCA since the beginning, and it was originally specified to use 32 bit IP addresses according to the IPv4 protocol. IPv4 supports 4 billion distinct IP addresses and in the emerging world of Internet of Everything and billions of interconnected devices, this is not enough. IPv6 uses 128 bit addresses, so more than 3.4 times ten-to-the-thirty-eighth power devices can be directly addressed. This new feature will be released as an Engineering Change Notice to the current revision of ATCA, Revision 3.0 This will get this much needed capability to the market quickly. The IPv6 feature is completely optional and does not affect backwards compatibility in any way. All existing compliant ATCA systems will remain so.

Other Hardware Platform Management Activities

The Hardware Platform Management (HPM) subcommittee started work in January, 2015 with a focus on enabling the PICMG HPM layer for Internet Protocol version 6 (IPv6). Prior to the work of this subcommittee, the PICMG HPM layer covered only IPv4.

The first step was to add IPv6 coverage for PICMG 3.0 R3.0, the ATCA Base specification and PICMG 3.7 R1.0, the ATCA Base Extensions specification. Extensions to both of these were accomplished via Engineering Change Notices (ECNs). ECNs go through all the formal PICMG specification review and adoption processes; once adopted, they formally amend the target specification.

An ECN for PICMG 3.0 to incorporate IPv6 was released April 20, 2015 It may be downloaded from the “AdvancedTCA” family page on this web site.

An ECN for PICMG 3.7 to incorporate IPv6 was released June 1, 2015 It may be downloaded from the “AdvancedTCA” family page on this web site.

The next step was a modest revision to HPM.2, the LAN-attached IPM Controller specification. That revision, R1.1, was also adopted in 2015. The subcommittee is now nearing completion of R2.0 for HPM.3, the DHCP-assigned Platform Management Parameters specification, which is undergoing Member Review as of March, 2016. This substantial revision adds support for version 6 of the Dynamic Host Configuration Protocol (DHCPv6), which complements IPv6.

As the number of Internet-connected entities in the IoT continues to grow exponentially and the workarounds that have allowed continued use of IPv4 are increasingly strained, new applications of ATCA and MicroTCA will increasingly need IPv6 support in the HPM layer.

COM Express           

This popular standard continues to be updated as improvements and changes to silicon continue. The subcommittee has been focused on support for four 10G KR interfaces with a new Type 7 pinout. Discussions have been around the total number of signals to support the 10G channels including interfaces for PHY configuration, LEDs and management. Simulation results are being reviewed to determine if ground guard banding is necessary for the high speed signals – there is one differential pair which runs at 10G. At this time the group is looking to reassign the DDI pins for the 10G signals. The expectation is that silicon that supports multiple 10G will likely be headless. The group would like to publish a preliminary pinout as soon as possible, likely by the end of March. Additional discussion centers around trying to harmonize the AB connector usage between new module types so that customers can easily migrate from Type 10 to Type 7. Increasing the existing Ethernet interface from 10/100/1000 Mb to 10G is also under consideration.

Physics Activities

The Physics community that developed ATCA 3.8 RTM extension and MTCA.4 with µRTM is very near to issuing a set of new hardware extensions called MTCA.4.1, introducing an additional rear backplane to support both precision analog and digital functions. The backplane supports ancillary Rear Power Modules that can deliver positive and negative analog power as well as standard power to µRTMs or full height eRTMS (extended RTMs). The additional backplane, side space and rear power makes possible a new family of applications, stimulated by the need for compact multi-GHz Low Level RF systems for high density superconducting accelerator applications. The extension document describes the backplane itself as a generic design adaptable by users to special functions if needed in a new connector zone. It also contains a special section defining Classes of RTMs to promote interoperability between AMCs and µRTMs among vendors. The first completed systems are now operational in the injector section of the new XFEL accelerator at DESY and several other laboratories are adopting the solution. Industry support of the critical support modules and infrastructure has been very good. The new standard for MTCA.4.1 is in final editing phase and will be submitted to PICMG very shortly for general member review. In addition four software guidelines which have been under development for several years are in final editing stages; these include Standard Device Model, Standard Hardware API, Standard Hot-Plug Procedure and Standard Process Model. All except the Standard Process Model are active and moving into final editing mode and are expected to be completed in the next few months.

Special thanks to committee chairs Justin Moll, Ray Larsen, Mark Overgaard, and Jeff Munch for these updates.