PICMG develops new standards and revises existing ones on an on-going basis.
New standards come to life when members identify the need to create a new embedded computing standard for a particular market or application. This is a structured process, but is relatively simple to initiate. All it takes to begin the development process is an initial Statement of Work, sponsored by three or more Executive members, that describes the market need and a rough proposal of what a standard addressing that might look like. The process is then opened up for all members to participate in the actual engineering work and development. The broad technical skill set of the membership and the one-company-one-vote rule provide an excellent environment for the creating of successful and relevant industry standards.
Existing standards are updated when appropriate. This might be because new technology becomes available that would improve the performance or lower the cost of compliant products. Existing standards are also extended when a new market or application is identified that requires new or additional features. These extensions are usually created in the form of subsidiary specifications that provide additional detail or enhancements.
Standards Recently Released or Currently Under Development:
The new COM specification under development is in parallel to existing COM Express efforts. The subcommittee will develop a next-generation COM standard and an accompanying Carrier Design Guide. The new specification is expected to support two different module types: one for high-performance computing, the other for embedded computing. Initial plans include incorporating a new high-speed connector able to support existing and future interfaces such as PCI Express Gen 5, and 100/200 Gb Ethernet. The specification will target medium to high-performance server-class processors.
Key COM-HPC Goals:
- Support for PCIe Gen 5.0 (32 Gb/s)
- 64 PCIe Lanes
- Min. 25 Gb Ethernet per signal pair to support 100 Gb Ethernet
- Update of other interfaces to latest technology levels
The goal is to have specifications ratified in early 2020. The team has elected Christian Eder of congatec as committee chair. Kontron’s Stefan Milnor is the technical editor and Dylan Lang of Samtec is the secretary.
PICMG is working with members and advisory board industry leaders to develop the elements for an IIoT specification. The effort centers around developing a meta-data model based on the DMTF’s RedFish® API. This master schema will adopt all types of individual companies’ data models so that devices on the factory floor can achieve true plug-and-play IIoT interoperability.
Check out our new IoT section and our vision paper Industrial IoT – A High Level Architectural Discussion for more details.
cPCI Serial for Space
cPCI Serial for Space provides a highly-ruggedized implementation for Space applications. It is intended to be used in Space, e.g. onboard satellites as the platform system and the payload controller as well as on Earth for the control systems and ground stations. Regular CompactPCI Serial products can be combined with cPCI Serial for Space products to develop test and simulation systems.
The four main components of cPCI Serial for Space are:
– Currently the CompactPCI Serial architecture supports full-mesh for Ethernet and star for PCI-Express. The new standard shall also support a dual star architecture to support redundancy.
– Beside Ethernet and PCI-Express also other serial interconnection like, the SpaceWire, SpaceFibre, TT-Ethernet and rapid I/O for inter-board communication shall be allowed.
– Provisions for high availability, e.g. a power distribution shall be defined, fault detection shall be explained and high availability of the system including the system management shall be specified.
– Environmental requirements for space shall be specified as well as special measures in case those are required.
One of the major goals is to keep the standard simple and understandable and to guarantee a maximum of interoperability between bus slots and boards. CPCI Serial for Space will help create highly sophisticated solutions for these emerging markets while re-using and evolving proven industrial technology.
High Speed Ethernet Fabrics for MicroTCA and AMC.2
This effort developed requirements that incorporate 10GBASE-KX4, 10GBASE-KR and 40GBASE-KR4 to the Common Option (ports 0 and 1), Fat Pipes (ports 4-7) and Extended Pipes (8-11) as defined in AMC.2 and used there and in all variants of MicroTCA. A key goal of this activity was to guarantee backward compatibility with existing MTCA and AMC mechanicals and connectors.
The “Higher Speed Ethernet Fabrics for MicroTCA.0 and AMC.1” group is working on bringing 40GbE to MicroTCA systems. The committee is currently working on completing signal integrity studies across the full interconnect channel. S-parameter models for the backplane and AMC have been developed and simulated and work on the MCH is being completed. Combinations of 90 and 110 ohm impedance signal pairs are being simulated in order to see the behavior of all corner cases. The committee will then compare the whole channel simulations with IEEE 40GBASE-KR4 requirements.
A 40G test backplane has already been designed and simulated as well as the AMC probe card. In the coming months, it is expected that all the simulation and characterization will be complete. From there, the MicroTCA.0 and AMC.1 specifications will be updated with the results, including the CRs (Change Requests) that have already been addressed. These documents will then be submitted to the broader membership for review and approval.
This popular standard continues to be updated as improvements and changes to silicon continue. Released in March of 2017, Revision 3.0 of COM Express provides for a new Type 7 connector and the addition of up to four 10 Gigabit Ethernet (10GbE) interfaces on the board. Previous revisions of the specification were limited to a single Gigabit Ethernet interface. The higher speed ports open up new markets such as data centers where the high compute density of COM Express can result in increased rack utilization. The 10GbE ports are also ideal for high bandwidth video applications such as surveillance. Another change to the specification includes increasing the number of PCI Express lanes to 32 across the Type 7 connector. This provides a wealth of connectivity and interface options including the ability to facilitate the use of GPGPUs.
The Physics community that developed ATCA 3.8 RTM extension and MTCA.4 with µRTM is very near to issuing a set of new hardware extensions called MTCA.4.1, introducing an additional rear backplane to support both precision analog and digital functions. The backplane supports ancillary Rear Power Modules that can deliver positive and negative analog power as well as standard power to µRTMs or full height eRTMS (extended RTMs). The additional backplane, side space and rear power makes possible a new family of applications, stimulated by the need for compact multi-GHz Low Level RF systems for high density superconducting accelerator applications. The extension document describes the backplane itself as a generic design adaptable by users to special functions if needed in a new connector zone. It also contains a special section defining Classes of RTMs to promote interoperability between AMCs and µRTMs among vendors.
The first completed systems are now operational in the injector section of the new XFEL accelerator at DESY and several other laboratories are adopting the solution. Industry support of the critical support modules and infrastructure has been very good. The new standard for MTCA.4.1 is in final editing phase and will be submitted to PICMG very shortly for general member review. In addition, four software guidelines which have been under development for several years have been finalized; these include Standard Device Model, Standard Hardware API, Standard Hot-Plug Procedure and Standard Process Model.